1. Field of the Invention
The present invention relates to vertical deflection circuits of television receivers, and more particularly to a vertical deflection circuit capable of preventing jitter of the picture on the screen in the vertical direction.
2. Description of the Prior Art
One of the major causes which detract from the quality of pictures on the screen of a television receiver is jitter. Being a phenomenon of unstable or wavering picture reproduction on the screen, jitter not only disturbs the pleasure of those watching television but is often suspected as a failure originating in a breakdown of some parts in a television receiver set.
A cause of such jitter can be explained by the following explanation which will be described by referring to the appended drawings, FIGS. 1 through 3.
FIG. 1 is a circuit diagram showing a conventional vertical deflection circuit which comprises an integrator 24 used for producing the vertical trigger signal and vertical oscillator 23. The integrator 24 is constructed by a first stage integrator of resistor 1 and capacitor 2 and a second stage integrator of resistor 3 and capacitor 4. The composite signal is fed into the integrator 24 through the input terminal 25, and thus the vertical trigger signal is obtained from the composite signal. The vertical trigger signal is applied to the vertical oscillator 23 through the coupling capacitor 22, and the saw-tooth wave is obtained from the output terminal 26.
Referring now to FIG. 2 (a), the composite synchronizing signal has equalizing pulse periods 100 and 300, vertical pulse period 200 and horizontal pulse period 400. After such composite synchronizing signal is applied to the integrator 24, vertical trigger signal 500 caused by synchronizing pulse 200 and excessive signal 600 caused by equalizing pulse 100 are obtained, as shown in FIG. 2 (b).
FIG. 3 shows the relationship among the vertical trigger signals P.sub.1, P.sub.2 and P.sub.3, voltages R.sub.1 and R.sub.2 at one end of the capacitor in the vertical oscillator 23 and flyback pulses Q.sub.1, Q.sub.2 and Q.sub.3. The waveforms shown are partly enlarged for explanatory purposes.
At a free-running frequency approximately equal to the field frequency, the flyback pulse Q.sub.1 is generated synchronously with the excessive signal P.sub.el, before the vertical oscillator is triggered by the vertical trigger signal P.sub.1. In this state, the capacitor of the time constant circuit starts discharging. Thus, the flyback pulse Q.sub.1 is generated earlier than the normal occurence period. On the other hand, the pulse P.sub.1 is applied to the vertical oscillator to again discharge the capacitor. This prolongs the time for the capacitor voltage to reach Eu, with the result that the width of the pulse Q.sub.1 is increased. After discharging, the capacitor starts charging again. When the capacitor voltage approaches E.sub.L as charging progresses, the pulse Q.sub.2 is generated synchronously with the vertical trigger signal P.sub.2 and has a time width corresponding to the flyback time. Because the time taken by the capacitor voltage to reach E.sub.U is prolonged, the voltage R.sub.1 is kept high at the time corresponding to excessive signal P.sub.e2 which does not cause the triggering of vertical oscillator 23; therefore, normal synchronism is established in the next field at the vertical trigger signal P.sub.2 to enable the flyback pulse Q.sub.2 to be present for a normal period. In the subsequent field, however, the oscillator is triggered by the excessive signal P.sub.e3 due to the equalizing pulse component effected before the arrival of the vertical trigger pulse P.sub.3, resulting in an early occurence of a prolonged pulse Q.sub.3 as in the case of the vertical trigger pulse P.sub.1. In other words, normal synchronism is maintained only in the fields of even turns as shown in FIG. 3. Unless this problem is solved it is impossible to prevent jittering of pictures reproduced on the screen of a television receiver.